Continuing progress in integrated circuit (“IC”) technology continues to lead to higher and higher levels of circuit integration. This is a result of the computer industry's relentless drive toward higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits. As new generations of integrated circuit products are released, the functionality of those products increases while the number of components used to fabricate them decreases.
Semiconductor devices are constructed from a silicon or gallium arsenide wafer through a process that comprises a number of deposition, masking, diffusion, etching, and implanting steps. Usually, many individual devices are constructed on the same wafer. When the devices are separated into individual rectangular units, each takes the form of an IC die.
In order to connect a die with other circuitry, it is common to mount it on a leadframe or on a multi-chip module substrate that is surrounded by a number of contact connections. Each die has bonding pads that are then individually connected in a wire-bonding operation to the leadframe's contact connections, using extremely fine gold or aluminum wires. The assemblies are then completed by individually encapsulating them in molded plastic or ceramic bodies called “packages”. With continuing technology improvements, packages themselves are also achieving higher and higher density.
The chip scale package (“CSP”) is a popular package configuration in the semiconductor industry. The size of a CSP package is only slightly larger than the IC chip, or die, that it encapsulates. The CSP therefore saves considerable space over earlier, larger configurations. In addition, since the smaller CSP size shortens internal signal transmission paths, the CSP also improves product performance.
The chip carrying structures within a CSP commonly include a leadframe that provides mechanical support for the individual IC device die. The leadframe also provides interconnect lines that enable the die to be connected electrically to surrounding circuitry.
Since the CSP leadframe is usually low in cost and easy to work with, it has become a popular package configuration for consumer electronic products. Popular leadframe-based CSP's are the quad flat nolead (“QFN”) package, the micro leadframe package (“MLP”), and the bottom leaded package (“BLP”). Popular leadless CSP's include various flip chip style packages such as the ball grid array (“BGA”) and the slightly larger than IC carrier (“SLICC”). Leadless CSP's have the additional advantage of shorter signal transmission paths and lower signal attenuation.
A conventional semiconductor package is typically manufactured in quantity in an assembly process that requires a custom mold and a custom form tool. Thus, the tooling cost for manufacturing a new package can be high. Therefore, rather than creating a package that is optimized specifically for a given IC size and input/output (“I/O”) configuration, a designer often compromises by selecting an already available package instead. The selection is done by matching the size and I/O terminal requirements of the IC as closely as possible to available packages for which the tooling investment has already been made. In such a case, unfortunately, the resulting package is optimized for neither density nor material cost.
During manufacturing of semiconductor packages, they are typically connected together either in an array or in a strip configuration. The individual packages must then be separated from each other. The separation process is referred to as “singulation”. Contemporary singulation uses either a sawing process or a punching process to separate the individual semiconductor packages. Punch singulation and saw singulation technologies are efficient and well developed.
However, there are still significant disadvantages with both punch singulation and saw singulation. For example, punch singulation wastes leadframe space (circuit area), can suffer from debris damage, and requires molds and singulation dies that are individually sized for each leadframe body size. This causes increased tooling investments or suboptimized design compromises. Saw singulation processes can form voids, can suffer strip warpage from differences in the thermal expansion of the material layers used, and can be impaired by materials that outgas.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.